In integrated circuit technology, it is necessary to separate the active regions of active devices (the "moat regions") from one another. In LSI and VLSI integrated circuits using MOS technology, isolation of active regions is usually accomplished by LOCOS (Local Oxidation of Silicon). To perform LOCOS, a patterned nitride on top of a thin oxide stack is used to cover the areas of a silicon substrate which will be the moat regions. By exposing the uncovered regions of the silicon substrate to a high temperature oxidizing ambient, a relatively thick field oxide is grown only in the exposed regions.
However, the LOCOS technique grows field oxide not only vertically in the exposed silicon regions, but also laterally underneath the edges of the nitride mask. This lateral oxide encroachment under the nitride, known as "birds-beak," can grow to a thickness of about half the field oxide thickness; thus, substantial real estate is wasted in this isolation technology. With the standard LOCOS process, the field oxide thickness has to be scaled down appropriately in order to reduce the birds-beak, otherwise, the remaining moat region will be inadequate for active device fabrication. The reduction in field oxide thickness, however, degrades the circuit performance because of increased interconnect capacitance. In addition, the leakage current under the field oxide and between adjacent moat regions increases rapidly with decreasing oxide thickness for a given voltage applied to a conductor passing over the field oxide, resulting in poor isolation between adjacent moats.
Several isolation techniques have been developed for reducing the amount of oxide encroachment in the standard LOCOS process. An isolation technology known as SWAMI (Sidewall Masked Isolation) uses a silicon etch and sidewall nitride layer (a layer of silicon nitride formed on the sides of the recessed silicon region) to suppress the lateral encroachment of the field oxide. The key aspect for the near-zero encroachment is the presence of the sidewall nitride, which is lifted up during growth of the field oxide. While the SWAMI process reduces encroachment of the field oxide, it too has limitations. One limitation is the tendency of the oxidation mask (deposited after the sidewall nitride layer) to fail at the but joint between the first nitride layer and the sidewall nitride layer. This failure occurs mainly due to the normal over-etching during the sidewall process and is evidenced by the localized encroachment of the field oxide, particularly at the corners of the patterns. Another limitation of the conventional SWAMI process is its increased sensitivity to defect generation in the silicon substrate due to the presence of the sidewall nitride. Another limitation is the double threshold that occurs in transistor characteristics due to a region adjacent to a moat having a relatively thin oxide, but which does not contain sufficient channel stop impurity.
A modification of the SWAMI process, modified fully-framed-fully-recessed (MF.sup.3 R) isolation, reduces the limitations of SWAMI. After the nitride, oxide, and recessed silicon layers are patterned and etched, the process uses an "undercut and backfill" technique, in which the oxide layer is undercut laterally for about 200-1000 Angstroms by wet-etching. A second pad oxide and a subsequent conformable deposition of a sidewall nitride refills the undercut cavity, forming an increased joint area between the two nitride films. This increased area maintains the integrity of the nitride-to-nitride joint during the oxide/nitride/oxide sidewall etch and subsequent field oxidation. A major limitation of the MF.sup.3 R process is that the silicon can be recess-etched only to depths of about 2,000 Angstroms. This may result in inadequate isolation between active regions.
Another approach to device isolation is the buried oxide (BOX) process. In the BOX process, a stress relief oxide layer is grown, followed by a chemical vapor deposit (CVD) of silicon nitride. The nitride/oxide stack is then patterned and etched using standard lithographic techniques, as in the SWAMI process. The etch is followed by deposition of a thicker oxide layer. Although the CVD oxide layer fills up the recessed-etch silicon regions, the layer is not planarized since the oxide sinks into wide recessed-etched regions, creating depressions in the CVD oxide layer. In order to form a planarized surface, a second photoresist pattern is used to fill the depressions with photoresist material and a third photoresist is used to coat the entire surface, resulting in a fairly planarized surface. A photoresist/oxide etch is used to etch-back both the photoresist and the oxide at the same rate thus leaving a fairly planarized oxide surface after any remaining photoresist is stripped off.
The BOX process has two major problems. The first problem is that the process requires two lithographic masking steps, which increases the complexity of the process. Secondly, the BOX process employs a critical resist etch-back process. In practice, the thickness of the spun-on resist depends upon pattern area density; the photoresist layer will be thinner in highly packed regions. As a result, the etched surface will be non-uniform after the resist etch-back and the surface of some active regions may be significantly attacked by the etch.
From the foregoing, it may be seen that a need has arisen for an isolation technology which provides substantially planar surfaces in high yield quantities, without substantial moat encroachment of stress induced defects near the active regions. Furthermore, a need has arisen for an isolation technology capable of providing a substantially planar surface, while using only one mask for patterning purposes. Such improved isolation technique should be able to provide planarized surfaces for both narrow and wide recesses between moats.